The hardware accelerator controlled by direct memory access (DMA) is greatly influenced by the communication bandwidth from/to DRAM through on-chip buses. This paper proposes a novel performance estimation algorithm to optimize the communication schemes (CSs). which are defined by the number of direct memory access controllers (DMACs) and the bank allocation of DRAM. In order to facil... https://foldlyers.shop/product-category/general-testers/